During the bulk manufacture of integrated circuits (ICs), semiconductor manufacturing processes are subject to process variation that may affect the operation of resulting IC chips. Additionally, as semiconductor manufacturing processes move towards smaller and smaller feature sizes, such as 28 nanometers and below, parasitic resistance-capacitance (RC) elements in interconnect structures of the ICs have an increasing effect on the operation of the resulting ICs chips. The process variation and the parasitic RC elements may negatively impact yields, as well as the performance and the reliability of the resulting IC chips, such that the ICs may be designed to account for process variation and parasitic RC elements using computer simulation.